The present application claims priority to Japanese Application No. P10-126945 filed May 11, 1998, which applications are incorporated herein by reference to the extent permitted by law.
1. Field of the Invention
This invention relates to a method for manufacturing semiconductor devices and more particularly to a method for manufacturing semiconductor devices in which a semiconductor region is formed selectively on the surface of a semiconductor, an epitaxial layer is thereafter formed on the semiconductor, and various semiconductor regions are subsequently formed on the epitaxial layer.
2. Description of Related Art
Semiconductor devices which are manufactured by a method in which a semiconductor region of the conduction type opposite to that of a substrate formed on the semiconductor substrate surface or on the epitaxial layer surface of the substrate surface is formed, an epitaxial layer is thereafter formed on the semiconductor substrate or the epitaxial layer, and various semiconductor regions are formed successively on the epitaxial layer have been known. For example, a solid state image sensing device disclosed in Japanese Published Unexamined Patent Application No. Hei 9-331058 belongs to such a semiconductor device. FIG. 2 shows a cross sectional view of such a semiconductor device. In FIG. 2, reference numeral 1 denotes a solid state image sensing device, reference numeral 2 denotes an n-type semiconductor substrate, reference numeral 3 denotes an epitaxial layer of the same conduction type as the n-type semiconductor substrate 2 with a low impurity concentration, and reference numeral 4 denotes a p-type well formed selectively on the surface of the epitaxial layer 3. In FIG. 2, it is not obvious whether the well is formed selectively. However, the well is formed selectively. Reference numeral 5 denotes a p-type (or n-type, or intrinsic) semiconductor region containing a concentration impurity considerably lower than that of the well 4, which are formed by epitaxial growth. In the semiconductor region 5, various semiconductor regions 6 to 9, and 14 are formed, further a transfer electrode 16, an interlayer insulating film 18, and a shielding film 17 are formed on the semiconductor surface with interposition of a gate insulating film 15. The applicant of this invention proposed another solid state image sensing device which was technically related to this solid state image sensing device in Japanese Patent Application No. Hei 8-270456. The solid state image sensing device has a similar cross sectional structure as that shown in FIG. 2.
The most important component of the device is the epitaxial layer. The p-type well layer 4 is formed selectively on the surface of the epitaxial layer 3 which is the under layer of the semiconductor region 5, various semiconductor regions 6 to 9, and 14 are formed on the semiconductor region 5, and the positional relation between the p-type well layer 4 and the semiconductor regions 6 to 9 and 14 is required to be highly accurate and the positional relation between the semiconductor regions 6 to 9 and 14 is required to be controlled with a considerably high accuracy. In a conventional method for controlling the positional relation, the wafer alignment mark is formed on a semiconductor substrate and a semiconductor region is formed with reference to the wafer alignment mark, and wafer alignment is performed every time when various semiconductor regions 4, 6 to 9, and 14 are formed respectively (mask matching) by use of the alignment mark as an index.
FIG. 3A to FIG. 3D is sectional views for describing the outline of such a conventional method. First, as shown in FIG. 3A, a wafer alignment mark b is formed on the surface of a semiconductor substrate a, and then a semiconductor region c is formed selectively on the surface of the semiconductor substrate a by photolithography using the wafer alignment mark b as an index for mask matching as shown in FIG. 3B. Next, as shown in FIG. 3C, an epitaxial layer d is formed on the semiconductor substrate a. At that time, a wafer alignment mark bxe2x80x2 on which the above-mentioned wafer alignment mark b is reflected is formed concomitantly on the surface of the epitaxial layer d. Subsequently, as shown in FIG. 3D, a semiconductor region e is formed selectively on the epitaxial layer d by photolithography using the wafer alignment mark bxe2x80x2 as an index for mask matching. Of course, the number of semiconductor region e formed on the epitaxial layer d is not one, generally a plurality of semiconductor regions are formed, and a wafer alignment mark bxe2x80x2 is used as an index in wafer alignment every time respectively when the plurality of semiconductor regions are formed.
However, the conventional method for manufacturing semiconductor devices shown in FIG. 3 is disadvantageous in that the position of the wafer alignment mark bxe2x80x2 does not coincide with the position of the wafer alignment mark b, and the configuration of the wafer alignment mark bxe2x80x2 becomes different from that of the wafer alignment mark b, particularly the edge is rounded to cause optical misdetection. In detail, as described in a literature, for example, Electronics Material Series: Silicon Crystal and Doping, P86 to 89, when an epitaxial layer is formed on a substrate having a pit on the surface, a pit is formed concomitantly on the epitaxial layer which reflects the pit on the substrate, in such case, the pit on the epitaxial layer is different from the pit on the substrate in the position, configuration, and sharpness of the edge (edgy corner) (rounded). Such positional deviation and magnitude of rounding (decreased sharpness of the edge) depend on the growth temperature, growth pressure, type of silicon source, and growing rate.
Accordingly, in the conventional method, the wafer alignment mark bxe2x80x2 is rounded to cause reduced optical detectability. Therefore, it is difficult to enhance the control accuracy of the positional relation between a plurality of semiconductor regions formed on an epitaxial layer d because such wafer alignment mark bxe2x80x2 is used as an index in wafer alignment. This poor control accuracy has become a serious problem, because higher positional accuracy for positioning a plurality of semiconductor regions formed selectively on an epitaxial layer has been required with increasing integration of semiconductor devices such as solid state image sensing device and with increasing minimization of devices.
The present invention is accomplished to solve the problem, it is an object of the present invention to provide a way to control the positional relation between a plurality of semiconductor regions formed selectively on an epitaxial layer after forming of the epitaxial layer in a method for manufacturing semiconductor devices in which the epitaxial layer is formed on a semiconductor surface having a semiconductor region formed selectively, and then a plurality of semiconductor regions are formed successively on the epitaxial layer selectively.
In a method for manufacturing semiconductor devices described in claim 1, a first wafer alignment mark is formed on the semiconductor substrate surface to be served as the under layer of an epitaxial layer which will be formed subsequently, and the first wafer alignment mark is used as an index for wafer alignment for forming selectively a semiconductor region on the semiconductor, and a second wafer alignment mark is formed on the surface of the epitaxial layer after the epitaxial layer is formed, and the second wafer alignment mark is used as an index for wafer alignment for forming respective semiconductor regions on the epitaxial layer.
According to the method for manufacturing semiconductor devices described in claim 1, the second wafer alignment mark is formed on the surface of the epitaxial layer after the epitaxial layer is formed and the additional wafer alignment mark having the sharp edge is used for wafer alignment of the respective semiconductor regions which are formed on the epitaxial layer as an index. Thus, the positional relation between the respective semiconductor regions which are formed on the epitaxial layer is controlled with high accuracy.
The positional relation of the semiconductor region which is formed on the semiconductor surface to be served as an under layer of the epitaxial layer to the respective semiconductor regions which are formed on the epitaxial layer is controlled with some accuracy by a method in which the third wafer alignment mark formed on the semiconductor surface after the epitaxial layer is formed is positioned with reference to the third wafer alignment mark formed concomitantly when the epitaxial layer is formed on the surface of the epitaxial layer with reflection of the first wafer alignment mark which has been formed on the semiconductor surface before the epitaxial layer is formed as an index.
The second wafer alignment mark is formed on a different position from the first and third wafer alignment marks in the direction along the surface of the semiconductor and epitaxial layer.
According to a semiconductor device having a semiconductor region formed selectively on an epitaxial layer on a semiconductor surface on which a semiconductor regions is formed selectively described in claim 4, the semiconductor device has a first wafer alignment mark on the semiconductor surface and a second wafer alignment mark on the surface of the epitaxial layer on the different position from the first wafer alignment mark in the direction along the surface of the semiconductor and epitaxial layer.